This page is documenting a work in progress feature do not assume it is available on the mainline branch.

You may find it developed on a topic branch

Rationale

This blueprint document the effort to support recent POWER CPU, with attention to the new VSX instruction set, Endiannes and the ISA 2.07 additional extensions present in the POWER8 cpu.

Design

VSX

Introduced with the ISA 2.06 the VSX is an extension to the normal Altivec (or VMX) vector unit present in many recent PowerPC and POWER cpus. Among the many additions is worth mentioning first the support for unaligned load and store.

Endianness Support

PowerPC and POWER had been traditionally BigEndian systems and most of the codebase written for this class of CPU assumes it as the default and only endiannes.

The POWER8 CPU is LittleEndian by default, requiring additional attention while writing new code.

Ideally all the code should be tested on a big endian system (e.g. POWER7) and a little endian one (POWER8).

ISA 2.07

The POWER8 implements an extension to the VSX implementing further useful primitives (such as vector popcount) that could be leveraged.

Development process

Porting Altivec code

Libav has already a large corpus of optimizations geared towards Altivec. Sadly they cannot be used as is:

* vec_ld and vec_st require a further byteswap in LittleEndian mode or the vec_vsx_ld and vec_vsx_st should be used instead. * Unpacking arrays using vec_mergel between an array and a zero array requires to swap the order of operands

Writing new code

Endianness

VSX is supported by power7 and assuming VSX means LittleEndian is wrong. There are Oracle instances to ease testing.

ISA 2.07

POWER8-only instructions should not be used in the generic VSX codepaths.


CategoryBlueprint CategoryWIP